Boolean Techniques in Testing of Digital Circuits

Currently, Very Large Scale Integrated (VLSI) circuits and the resulting digital systems are widely used in almost all areas of human’s life. To ensure the validity of these systems, error-free VLSI circuits are becoming more and more important. With the increasing complexity of VLSI circuits, the cost for the test on VLSI circuits has risen dramatically. So it is necessary to reduce the cost of test. This thesis proposes two approaches to achieve this goal. One approach, used before manufacture, is to improve the circuit structure for a better testability. The other one, used after manufacture, is to improve the test tool for a higher efficiency of fault detection. In this thesis, Binary Decision Diagrams (BDDs) are used to improve the structure of VLSI circuits for a better testability. It has been proved that Automatic Test Pattern Generation (ATPG) for BDD circuits under the Stuck At Fault Model (SAFM), the Path Delay Fault Model (PDFM) and the Bridging Fault Model (BFM) can be carried out in polynomial time. A new technique that adds a new input and an inverter to BDD circuits has been presented. Using this technique, the testability of circuits under SAFM, PDFM and BFM can be greatly improved. Especially, under SAFM and PDFM, 100% testable circuits can be generated. On the other hand, a technique based on Boolean Satisfiability (SAT) is proposed to improve the efficiency of test tools. A SAT-based ATPG algorithm suited for large industrial circuits with tri-state elements has been presented. It can generate test patterns for the faults that are aborted by classical algorithms. The combination of a classical TPG stage and the SAT-based TPG stage has been integrated into an industrial ATPG tool. Experimental results have demonstrated the quality and efficiency of this combination.